الملخص
تعمل Evollabs Tech على تطوير خوادم مخصصة لتطبيقات الذكاء الاصطناعي والتعلّم الآلي. يتولى أخصائي تدفقات أدوات أتمتة تصميم الدوائر المتكاملة تطوير تدفقات التصميم وصيانتها من RTL إلى GDS، وإدارة أدوات EDA والتراخيص والبنية التحتية للحوسبة والتخزين، ودعم دمج وحدات IP. وتشمل المهام أتمتة الأعمال المتكررة، وإعداد لوحات المتابعة، وتوثيق منهجيات العمل وتدريب المهندسين بالتعاون مع فرق التصميم. يشترط مؤهل جامعي مناسب وخبرة لا تقل عن 7 سنوات في بيئات تصميم ASIC/SoC والبنية التحتية للتصميم، إلى جانب خبرة بأدوات EDA والبرمجة النصية وGit وCI/CD. الوظيفة بدوام كامل ومن مقر الشركة في دبي، الإمارات العربية المتحدة.
نص الإعلان
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Location: Dubai - UAE
Team: IT Infrastructure / DevOps
Type: Full-time - On-site
About Us
We are a tech company specializing in the design and development of cutting-edge, customized server hardware solutions optimized for artificial intelligence and machine learning applications.
Our mission is to empower businesses and researchers to accelerate their AI initiatives by providing them with high-performance, scalable, and energy-efficient hardware infrastructure.
As a rapidly growing company at the forefront of AI hardware innovation, we are constantly seeking talented and motivated individuals to join our team. We offer a dynamic and challenging work environment, with opportunities to make a significant impact on the future of AI technology.
Your Mission
As an ASIC EDA Flow Specialist, you will be responsible for architecting, developing, and maintaining the design flows and infrastructure that power our AI ASIC development. You will partner closely with RTL, verification, physical design, and CAD engineers to build robust, scalable, and efficient EDA environments that accelerate the path from RTL to silicon.
Your expertise will ensure our teams can innovate faster, with best-in-class automation, quality of results, and time-to-tape-out.
Responsibilities
Develop, maintain, and optimize ASIC EDA flows across front-end, back-end, and sign-off stages from RTL to GDS.
Manage EDA tool installations, updates, and license servers (FlexLM, RLM, SCL), including license forecasting, allocation, and vendor coordination.
Oversee compute grid and storage infrastructure, ensuring optimal job scheduling, resource utilization, and uptime for large-scale ASIC builds.
Architect and maintain Git-based infrastructure (GitLab) for design version control, CI/CD, and team collaboration.
Manage and support IP vendor tools, including evaluation, installation, and maintenance of vendor-specific environments (e.g., TSMC, ARM, Synopsys, Cadence).
Coordinate and track Soft and Hard IP integration within EDA flows, managing deliverables, versioning, and quality checks.
Maintain a central IP database with metadata (version, PDK, constraints, verification status) to streamline reuse across projects.
Collaborate with design teams to integrate third-party IPs into custom SoC flows and validate tool/IP compatibility.
Automate repetitive setup tasks (e.g., IP import, constraint generation, regression setup, reporting) to improve productivity.
Develop and maintain dashboards for EDA tool usage, license consumption, and compute/storage monitoring.
Document flow methodologies and provide internal training for new engineers.
Requirements (must-have)
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
7 + years of experience in ASIC/SoC design environment management, CAD/EDA flow development, or design infrastructure engineering.
Strong knowledge of EDA tools (Synopsys, Cadence, Siemens/Mentor) and their installation, configuration, and licensing.
Experience with EDA license servers (FlexLM, RLM, SCL) and usage optimization.
Proficiency in Tcl, Python, Yaml, and Shell scripting for automation and flow development.
Proficiency in Make, CMake, or Bazel-based orchestration frameworks for flow and regression builds.
Familiarity with compute grid management systems (LSF, SLURM, Grid Engine) and storage architecture for large ASIC projects.
Practical experience with Git and integration into design workflows.
Proficiency in CI/CD automation, pipelines, or internal build systems.
Strong communication, documentation, and problem-solving skills.
Nice-to-Have
Solid understanding of RTL-to-GDSII flow, timing/power trade-offs, and tool interactions.
Exposure to advanced process nodes (7 nm and below) and multi-die design methodologies.
Why Join Us
Work at the intersection of AI and silicon to enable breakthroughs that power the next generation of intelligent computing.
Join a highly experienced, fast-moving team that values technical depth, innovation, and hands-on impact.
Build and own EDA methodologies that directly influence silicon performance, cost, and scalability.
Enjoy an environment that rewards initiative, collaboration, and continuous learning.
Competitive compensation, growth opportunities, and the chance to shape the core infrastructure behind cutting-edge AI ASICs.
Ready to Accelerate the Future of AI?
If you’re passionate about building world-class design flows and enabling engineers to push the limits of silicon performance, we’d love to hear from you.
Apply now and join us on our journey to redefine AI hardware performance at scale.