Summary
Evollabs Tech develops customized server hardware for AI and machine-learning applications. The Senior Physical Design Engineer will lead block- or subsystem-level implementation from netlist handoff through physical verification and signoff, including floorplanning, place-and-route, timing closure, and PPA optimization. The role requires at least 7 years of hands-on ASIC or SoC physical design experience, advanced-node design and tapeout experience, and proficiency with industry-standard EDA tools and scripting. This is a full-time, on-site position in Dubai, UAE.
The posting
As published on evollabs.tech. Pulled from the employer's site and shown as they wrote it.
Location: Dubai - UAE
Team: SoC Physical Design Team
Type: Full-time – On-site
About Us
We are a tech company specializing in the design and development of cutting-edge, customized server hardware solutions optimized for artificial intelligence and machine learning applications. Our mission is to empower businesses and researchers to accelerate their AI initiatives by providing them with high-performance, scalable, and energy-efficient hardware infrastructure.
As a rapidly growing company at the forefront of AI hardware innovation, we are constantly seeking talented and motivated individuals to join our team. We offer a dynamic and challenging work environment with opportunities to make a significant impact on the future of AI.
Role Overview
We are seeking a Senior Physical Design Engineer to drive physical implementation of advanced AI SoC / ASIC accelerator designs. This role will own complex blocks and subsystems from RTL/netlist handoff through floorplanning, place-and-route, timing closure, physical verification, and signoff.
The ideal candidate has strong experience with advanced-node physical design, production tapeouts, PPA optimization, and cross-functional execution across RTL, verification, DFT, architecture, and signoff teams.
Responsibilities
Own block-level or subsystem-level physical design from netlist to GDS.
Drive floorplanning, placement, CTS, routing, optimization, ECOs, and signoff closure.
Develop floorplans for compute clusters, memory subsystems, NoCs, clocking structures, and high-speed interface blocks.
Close timing across multiple modes and corners, including setup, hold, skew, generated clocks, and SI-aware timing.
Optimize designs for performance, power, area, routability, and manufacturability.
Support power planning, IR drop, EM, extraction, and reliability closure.
Execute physical verification, including DRC, LVS, antenna, ERC, density, and metal fill.
Collaborate with RTL, architecture, verification, DFT, and packaging, teams to resolve implementation issues.
Support integration of complex IPs such as NoC, PCIe, Ethernet, UCIe, HBM/GDDR, PLLs, CPUs, GPUs, NPUs, or custom AI accelerators.
Develop scripts and methodology improvements to improve implementation efficiency, reporting, and design quality.
Minimum Qualifications
7+ years of hands-on experience in ASIC or SoC physical design.
Experience taking complex blocks or subsystems through physical signoff.
Strong knowledge of floorplanning, place-and-route, CTS, STA, ECO, and signoff flows.
Experience with advanced-node, high-frequency, or high-density designs.
Strong understanding of SDC, setup/hold timing, multi-mode multi-corner analysis, and clock-tree optimization.
Experience with physical verification and signoff, including DRC, LVS, IR drop, EM, and extraction.
Experience integrating complex IPs such as NoC, CPU, GPU/NPU, PCIe, Ethernet, UCIe, HBM/GDDR, or other high-speed interfaces.
Familiarity with multiple clock domains, asynchronous interfaces, generated clocks, and PLL integration.
Proficiency with industry-standard EDA tools such as Synopsys ICC2/Fusion Compiler, PrimeTime, StarRC, Cadence Innovus, Tempus, Voltus, RedHawk, Calibre, or equivalent.
Strong scripting skills in Tcl, Python, Perl, or shell.
Strong debugging, communication, and cross-functional collaboration skills.
Preferred Qualifications
Experience with AI accelerators, GPUs, NPUs, or highly parallel compute architectures.
Experience with HBM/GDDR, chiplets, UCIe, 2.5D packaging, or package-aware physical design.
Experience with DFT-aware physical implementation, scan reordering, MBIST/LBIST, and test-mode timing.
Prior tapeout experience on advanced-node SoCs.
What Success Really Means
First silicon boots and runs real AI workloads, not just benchmarks.
PPA targets are met, with performance per watt competitive with industry leaders.
Timing, power, physical verification, and reliability signoff are completed with high quality and predictable execution.
Compiler, firmware, and system teams can use the hardware efficiently without physical-design-driven workarounds.
Critical silicon or customer issues can be debugged and root-caused quickly, with a target mean time to debug of less than 24 hours.
Ready to accelerate the future of AI?
Submit your application and show us how you think systematically about physical design, PPA closure, and building silicon that scales.
Join us in our mission to democratize AI compute — where your physical design expertise becomes the foundation of tomorrow’s AI breakthroughs.